報告人：Prof. Chia-Wen Lin (林嘉文), National Tsing Hua University, Taiwan
摘要：Traditionally, after ID circuit design and layout, it takes months to fabricate an IC wafer, involving a multiple-step sequence of photolithographic and chemical processing. In this talk, we will show how deep-learning-based image prediction can assist IC design for manufacturability. To this end, we formulate the lithography and etching processes of metal layers as a set of nonlinear warping functions between a patch of IC layout pattern and its corresponding SEM image, and models the set of warping functions using a CNN-based LithoNet parametrized with IC fabrication parameters.
報告人簡介：Prof. Chia-Wen Lin received his PhD degree in Electrical Engineering from National Tsing Hua University (NTHU), Hsinchu, Taiwan in 2000. He is currently a Professor with the Department of Electrical Engineering, NTHU, Taiwan. He also serves as Deputy Director of the AI Research Center of NTHU, and Director of Multimedia Technology Research Center of the EECS College, NTHU. His research interests include image/video processing, computer vision, and video networking.Dr. Lin is an IEEE Fellow. He is a Distinguished Lecturer of IEEE Circuits and Systems Society (CASS) during 2018-2019. He is serving as President of Chinese Image Processing and Pattern Recognition Association, Taiwan (term: 2019-2020). He has served as Associate Editor of IEEE Transactions on Image Processing, IEEE Transactions on Multimedia, IEEE Transactions on Circuits and Systems for Video Technology, and IEEE Multimedia. He served as a Steering Committee member of the IEEE Transactions on Multimedia during 2013-2015. He was Chair of the Multimedia Systems and Applications Technical Committee of the IEEE CASS. He has served as TPC Chair of IEEE ICME in 2010 and IEEE ICIP in 2019, and the Conference Chair of IEEE VCIP in 2018. His papers won the Best Paper Award of IEEE VCIP 2015, and the Young Investigator Award of VCIP 2005.